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ISCA
2008
IEEE
150views Hardware» more  ISCA 2008»
13 years 12 months ago
Fetch-Criticality Reduction through Control Independence
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from th...
Mayank Agarwal, Nitin Navale, Kshitiz Malik, Matth...
IPPS
2006
IEEE
13 years 11 months ago
Improving cache locality for thread-level speculation
With the advent of chip-multiprocessors (CMPs), Thread-Level Speculation (TLS) remains a promising technique for exploiting this highly multithreaded hardware to improve the perfo...
Stanley L. C. Fung, J. Gregory Steffan
PODC
1997
ACM
13 years 9 months ago
Implementing Wait-Free Objects on Priority-Based Systems
Wait-free objects are often implemented through the use of a \helping scheme", whereby one process \helps" one or more other processes to complete an operation. This pap...
James H. Anderson, Srikanth Ramamurthy, Rohit Jain
SI3D
1992
ACM
13 years 9 months ago
Interactive Volume Rendering on a Multicomputer
Direct volume rendering is a computationally intensive operation that has become a valued and often preferred visualization tool. For maximal data comprehension, interactive manip...
Ulrich Neumann
ISPASS
2010
IEEE
14 years 10 days ago
The Hadoop distributed filesystem: Balancing portability and performance
—Hadoop is a popular open-source implementation of MapReduce for the analysis of large datasets. To manage storage resources across the cluster, Hadoop uses a distributed user-le...
Jeffrey Shafer, Scott Rixner, Alan L. Cox