7 search results - page 2 / 2 » Exploiting level sensitive latches in wire pipelining |
HPCA
2005
IEEE
13 years 10 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
ASPDAC
2005
ACM
13 years 6 months ago
2005
ACM
— As microprocessor technology continues to scale into the nanometer regime, recent studies show that interconnect delay will be a limiting factor for performance, and multiple c...