41 search results - page 3 / 9 » Exploiting program cyclic behavior to reduce memory latency ... |
HPCA
2006
IEEE
14 years 5 months ago
2006
IEEE
Building processors with large instruction windows has been proposed as a mechanism for overcoming the memory wall, but finding a feasible and implementable design has been an elu...
CASES
2003
ACM
13 years 10 months ago
2003
ACM
Bank locality can be defined as localizing the number of load/store accesses to a small set of memory banks at a given time. An optimizing compiler can modify a given input code t...
ECRTS
2007
IEEE
13 years 11 months ago
2007
IEEE
Many embedded systems feature processors coupled with a small and fast scratchpad memory. To the difference with caches, allocation of data to scratchpad memory must be handled by...
EUROPAR
2009
Springer
13 years 8 months ago
2009
Springer
The Cell Broadband Engine (Cell BE) is a heterogeneous multi-core processor specifically designed to exploit thread-level parallelism. Its memory model comprehends a common shared ...
ASPDAC
2004
ACM
13 years 10 months ago
2004
ACM
The design of future high-performance embedded systems is hampered by two problems: First, the required hardware needs more energy than is available from batteries. Second, curren...