41 search results - page 7 / 9 » Exploiting program cyclic behavior to reduce memory latency ... |
CF
2005
ACM
13 years 8 months ago
2005
ACM
Modern microprocessor designs continue to obtain impressive performance gains through increasing clock rates and advances in the parallelism obtained via micro-architecture design...
CASES
2009
ACM
14 years 20 days ago
2009
ACM
Embedded processors have become increasingly complex, resulting in variable execution behavior and reduced timing predictability. On such processors, safe timing specifications e...
ISCAPDCS
2003
13 years 7 months ago
2003
This paper presents the Dynamic Simultaneous Multithreaded Architecture (DSMT). DSMT efficiently executes multiple threads from a single program on a SMT processor core. To accomp...
ASPLOS
2008
ACM
13 years 8 months ago
2008
ACM
Parallel and concurrent garbage collectors are increasingly employed by managed runtime environments (MREs) to maintain scalability, as multi-core architectures and multi-threaded...
CASES
2010
ACM
13 years 4 months ago
2010
ACM
The performance of most embedded systems is critically dependent on the memory hierarchy performance. In particular, higher cache hit rate can provide significant performance boos...