41 search results - page 8 / 9 » Exploiting program cyclic behavior to reduce memory latency ... |
ISCA
2000
IEEE
13 years 9 months ago
2000
IEEE
For many applications, branch mispredictions and cache misses limit a processor’s performance to a level well below its peak instruction throughput. A small fraction of static i...
IEEEPACT
2005
IEEE
13 years 11 months ago
2005
IEEE
Dynamic optimization has the potential to adapt the program’s behavior at run-time to deliver performance improvements over static optimization. Dynamic optimization systems usu...
ISLPED
2005
ACM
13 years 11 months ago
2005
ACM
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called Cluster of Active Disks (CAD), where the storag...
HPCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Future CMPs will combine many simple cores with deep cache hierarchies. With more cores, cache resources per core are fewer, and must be shared carefully to avoid poor utilization...
TJS
2002
13 years 5 months ago
2002
Historically, compilers have operated by applying a fixed set of optimizations in a predetermined order. We call such an ordered list of optimizations a compilation sequence. This...