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» Exploiting regularity for low-power design
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JCP
2008
324views more  JCP 2008»
13 years 5 months ago
Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell
In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regula...
Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, A...
ISLPED
2004
ACM
124views Hardware» more  ISLPED 2004»
13 years 10 months ago
The design of a low power asynchronous multiplier
In this paper we investigate the statistics of multiplier operands and identify two characteristics of their distribution that have important consequences for the design of low po...
Yijun Liu, Stephen B. Furber
AVSS
2009
IEEE
13 years 2 months ago
Multimodal Abandoned/Removed Object Detection for Low Power Video Surveillance Systems
Low-cost and low-power video surveillance systems based on networks of wireless video sensors will enter soon the marketplace with the promise of flexibility, quick deployment an...
Michele Magno, Federico Tombari, Davide Brunelli, ...
ATS
1997
IEEE
89views Hardware» more  ATS 1997»
13 years 9 months ago
Guaranteeing Testability in Re-encoding for Low Power
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...
ICCAD
2000
IEEE
188views Hardware» more  ICCAD 2000»
13 years 9 months ago
Bus Optimization for Low-Power Data Path Synthesis Based on Network Flow Method
— Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral l...
Sungpack Hong, Taewhan Kim