Low-Power and High-Performance 1-Bit CMOS Full-Adder Cell

In this paper a new low power and high performance adder cell using a new design style called "Bridge" is proposed. The bridge design style enjoys a high degree of regularity, higher density than conventional CMOS design style as well as lower power consumption, by using some transistors, named bridge transistors. Simulation results illustrate the superiority of the resulting proposed adder against conventional CMOS 1-bit full-adder in terms of power, delay and PDP. We have performed simulations using HSPICE in a 90 nanometer (nm) standard CMOS technology at room temperature; with supply

• Type: Journal
• Year: 2008
• Where: JCP
• Authors: Keivan Navi, Omid Kavehie, Mahnoush Rouholamini, Amir Sahafi, Shima Mehrabi, Nooshin Dadkhahi
• Keywords: Conventional Cmos, Design Style, JCP 2008, Performance Adder Cell