27 search results - page 3 / 6 » Exploiting spatial parallelism in Ethernet-based cluster int... |
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
PVM
2005
Springer
13 years 10 months ago
2005
Springer
Parallel execution of simulation runs has become indispensable in different research areas recently. One of the most promising and powerful models in science are cellular automata ...
ASPLOS
1998
ACM
13 years 9 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
IPPS
2009
IEEE
13 years 12 months ago
2009
IEEE
The increasing demand for computational cycles is being met by the use of multi-core processors. Having large number of cores per node necessitates multi-core aware designs to ext...
IPPS
1999
IEEE
13 years 9 months ago
1999
IEEE
Existing low-latency protocols make unrealistically strong assumptions about reliability. This allows them to achieve impressive performance, but also prevents this performance bei...