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» Exploiting the Parallelism Exposed by Partial Evaluation
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MICRO
1995
IEEE
217views Hardware» more  MICRO 1995»
13 years 8 months ago
Improving instruction-level parallelism by loop unrolling and dynamic memory disambiguation
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
Jack W. Davidson, Sanjay Jinturkar
IFL
2004
Springer
131views Formal Methods» more  IFL 2004»
13 years 10 months ago
Exploiting Single-Assignment Properties to Optimize Message-Passing Programs by Code Transformations
The message-passing paradigm is now widely accepted and used mainly for inter-process communication in distributed memory parallel systems. However, one of its disadvantages is the...
Alfredo Cristóbal-Salas, Andrey Chernykh, E...
FPGA
2001
ACM
123views FPGA» more  FPGA 2001»
13 years 9 months ago
Matching and searching analysis for parallel hardware implementation on FPGAs
Matching and searching computations play an important role in the indexing of data. These computations are typically encoded in very tight loops with a single index variable and a...
Pablo Moisset, Pedro C. Diniz, Joonseok Park
QEST
2007
IEEE
13 years 11 months ago
A Petri Net Model for Evaluating Packet Buffering Strategies in a Network Processor
Previous studies have shown that buffering packets in DRAM is a performance bottleneck. In order to understand the impediments in accessing the DRAM, we developed a detailed Petri...
Girish B. C., R. Govindarajan
SAMOS
2004
Springer
13 years 10 months ago
Modeling Loop Unrolling: Approaches and Open Issues
Abstract. Loop unrolling plays an important role in compilation for Reconfigurable Processing Units (RPUs) as it exposes operator parallelism and enables other transformations (e.g...
João M. P. Cardoso, Pedro C. Diniz