13 search results - page 3 / 3 » Exploiting the locality of memory references to reduce the a... |
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
MICRO
2003
IEEE
13 years 10 months ago
2003
IEEE
High-performance caches statically pull up the bitlines in all cache subarrays to optimize cache access latency. Unfortunately, such an architecture results in a significant wast...
HPCA
2008
IEEE
14 years 5 months ago
2008
IEEE
Hard-to-predict branches depending on longlatency cache-misses have been recognized as a major performance obstacle for modern microprocessors. With the widening speed gap between...