12 search results - page 2 / 3 » Exploring High Bandwidth Pipelined Cache Architecture for Sc... |
MICRO
2003
IEEE
13 years 11 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
CASES
2008
ACM
13 years 7 months ago
2008
ACM
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
FCCM
1999
IEEE
13 years 10 months ago
1999
IEEE
Technology scaling of CMOS processes brings relatively faster transistors (gates) and slower interconnects (wires), making viable the addition of reconfigurability to increase per...
ICS
2005
Tsinghua U.
13 years 11 months ago
2005
Tsinghua U.
Parallel I/O needs to keep pace with the demand of high performance computing applications on systems with ever-increasing speed. Exploiting high-end interconnect technologies to ...
SIGCOMM
2010
ACM
13 years 6 months ago
2010
ACM
Data-intensive applications that operate on large volumes of data have motivated a fresh look at the design of data center networks. The first wave of proposals focused on designi...