33 search results - page 2 / 7 » Exploring Performance Tradeoffs for Clustered VLIW ASIPs |
ICCD
2005
IEEE
14 years 2 months ago
2005
IEEE
Presently, Architecture Description Languages (ADLs) are widely used to raise the abstraction level of the design space exploration of Application Specific Instruction-set Proces...
HPCA
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper represents a design study of the datapath for a very long instruction word (VLIW) video signal processor (VSP). VLIW architectures provide high parallelism and excellen...
ASPDAC
2004
ACM
13 years 11 months ago
2004
ACM
— For multimedia applications, loop buffering is an efficient mechanism to reduce the power in the instruction memory of embedded processors. In particular, software controlled ...
CAMP
2005
IEEE
13 years 7 months ago
2005
IEEE
Abstract— In this paper we address the problem of the architectural exploration from the energy/performance point of view of a VLIW processor for embedded systems. We also consid...
DAC
2001
ACM
14 years 6 months ago
2001
ACM
Clustering is an effective method to increase the available parallelism in VLIW datapaths without incurring severe penalties associated with large number of register file ports. E...