33 search results - page 1 / 7 » Exploring Wakeup-Free Instruction Scheduling |
HPCA
2004
IEEE
14 years 5 months ago
2004
IEEE
Design of wakeup-free issue queues is becoming desirable due to the increasing complexity associated with broadcast-based instruction wakeup. The effectiveness of most wakeup-free...
LCTRTS
1998
Springer
13 years 9 months ago
1998
Springer
Instruction scheduling is a necessary step in compiling for many modern microprocessors. Traditionally, global instruction scheduling techniques have outperformed local techniques....
ASPLOS
2006
ACM
13 years 9 months ago
2006
ACM
This paper explores hierarchical instruction scheduling for a tiled processor. Our results show that at the top level of the hierarchy, a simple profile-driven algorithm effective...
ISCA
1998
IEEE
13 years 9 months ago
1998
IEEE
For maximum performance, an out-of-order processor must issue load instructions as early as possible, while avoiding memory-order violations with prior store instructions that wri...
DATE
2008
IEEE
13 years 11 months ago
2008
IEEE
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized ins...