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» Exploring the Limits of Sub-Word Level Parallelism
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ISCA
2010
IEEE
232views Hardware» more  ISCA 2010»
13 years 4 months ago
Evolution of thread-level parallelism in desktop applications
As the effective limits of frequency and instruction level parallelism have been reached, the strategy of microprocessor vendors has changed to increase the number of processing ...
Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mu...
CAMP
2005
IEEE
13 years 11 months ago
Real-Time Low Level Feature Extraction for On-Board Robot Vision Systems
Abstract— Robot vision systems notoriously require large computing capabilities, rarely available on physical devices. Robots have limited embedded hardware, and almost all senso...
Roberto Pirrone, Giuseppe Careri, F. Saverio Fabia...
ICPP
2009
IEEE
14 years 9 days ago
Accelerating Checkpoint Operation by Node-Level Write Aggregation on Multicore Systems
—Clusters and applications continue to grow in size while their mean time between failure (MTBF) is getting smaller. Checkpoint/Restart is becoming increasingly important for lar...
Xiangyong Ouyang, Karthik Gopalakrishnan, Dhabales...
ASPDAC
2005
ACM
102views Hardware» more  ASPDAC 2005»
13 years 7 months ago
A framework for automated and optimized ASIP implementation supporting multiple hardware description languages
— Architecture Description Languages (ADLs) are widely used to perform design space exploration for Application Specific Instruction Set Processors (ASIPs). While the design spa...
Oliver Schliebusch, Anupam Chattopadhyay, David Ka...
ACMSE
2006
ACM
13 years 7 months ago
Tic-Tac-LEGO: an investigation into coordinated robotic control
The Lego Mindstorms Robot Command eXplorer (RCX) is a popular robotics kit that provides an immediate "out-of-the-box" opportunity to explore software controlled robot i...
Ruben Vuittonet, Jeff Gray