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ICPP
2008
IEEE
14 years 14 days ago
Machine Learning Models to Predict Performance of Computer System Design Alternatives
Computer manufacturers spend a huge amount of time, resources, and money in designing new systems and newer configurations, and their ability to reduce costs, charge competitive p...
Berkin Özisikyilmaz, Gokhan Memik, Alok N. Ch...
CEC
2010
IEEE
13 years 6 months ago
Parallel hybrid evolutionary algorithms on GPU
Abstract— Over the last years, interest in hybrid metaheuristics has risen considerably in the field of optimization. Combinations of methods such as evolutionary algorithms and...
Thé Van Luong, Nouredine Melab, El-Ghazali ...
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
14 years 2 days ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
13 years 8 months ago
Translation caching: skip, don't walk (the page table)
This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page t...
Thomas W. Barr, Alan L. Cox, Scott Rixner
CASES
2008
ACM
13 years 8 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi