30 search results - page 1 / 6 » Exploring the interplay of yield, area, and performance in p... |
ICCD
2007
IEEE
14 years 1 months ago
2007
IEEE
The deployment of future deep submicron technology calls for a careful review of existing cache organizations and design practices in terms of yield and performance. This paper pr...
DATE
2003
IEEE
13 years 10 months ago
2003
IEEE
In this paper we propose a design technique to pipeline cache memories for high bandwidth applications. With the scaling of technology cache access latencies are multiple clock cy...
FCCM
2008
IEEE
13 years 11 months ago
2008
IEEE
As FPGA-based systems including soft-processors become increasingly common we are motivated to better understand the best way to scale the performance of such systems. In this pap...
ISCA
2002
IEEE
13 years 9 months ago
2002
IEEE
One architectural method for increasing processor performance involves increasing the frequency by implementing deeper pipelines. This paper will explore the relationship between ...
ICCD
2006
IEEE
14 years 1 months ago
2006
IEEE
Abstract— The continuing divergence of processor and memory speeds has led to the increasing reliance on larger caches which have become major consumers of area and power in embe...