21 search results - page 2 / 5 » Extending Automatic Parallelization to Optimize High-Level A... |
IISWC
2009
IEEE
14 years 17 hour ago
2009
IEEE
Abstract—Dynamic runtimes can simplify parallel programming by automatically managing concurrency and locality without further burdening the programmer. Nevertheless, implementin...
ICS
2009
Tsinghua U.
14 years 4 days ago
2009
Tsinghua U.
The Cell BE is a multicore processor with eight vector accelerators (called SPEs) that implement explicit cache management through direct memory access engines. While the Cell has...
IEEEPACT
2009
IEEE
14 years 17 hour ago
2009
IEEE
Abstract—Load elimination is a classical compiler transformation that is increasing in importance for multi-core and many-core architectures. The effect of the transformation is ...
FCCM
2011
IEEE
12 years 9 months ago
2011
IEEE
—The problem of automatically generating hardware modules from a high level representation of an application has been at the research forefront in the last few years. In this pap...
HPCA
2009
IEEE
14 years 5 months ago
2009
IEEE
Heterogeneous multicores, such as Cell BE processors and GPGPUs, typically do not have caches for their accelerator cores because coherence traffic, cache misses, and latencies fr...