102 search results - page 1 / 21 » Fair Queuing Memory Systems |
MICRO
2006
IEEE
13 years 11 months ago
2006
IEEE
We propose and evaluate a multi-thread memory scheduler that targets high performance CMPs. The proposed memory scheduler is based on concepts originally developed for network fai...
ISPAN
2005
IEEE
13 years 10 months ago
2005
IEEE
Most high-end switches use an input-queued or a combined input- and output-queued architecture. The switch fabrics of these architectures commonly use an iterative scheduling syst...
RTSS
2002
IEEE
13 years 9 months ago
2002
IEEE
In this paper, we present the first end-to-end fairness analysis of a network of fair servers. We argue that it is difficult to extend existing single-node fairness analysis to ...
ISCA
2011
IEEE
12 years 8 months ago
2011
IEEE
Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these share...
HOTI
2005
IEEE
13 years 10 months ago
2005
IEEE
Modern routers and switch fabrics can have hundreds of input and output ports running at up to 10 Gb/s; 40 Gb/s systems are starting to appear. At these rates, the performance of ...