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» Fanout optimization under a submicron transistor-level delay...
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ISQED
2002
IEEE
126views Hardware» more  ISQED 2002»
13 years 10 months ago
Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning
As the process technology advances into the deep submicron era, interconnect plays a dominant role in determining circuit performance. Buffer insertion/sizing and wire sizing are ...
Nicholas Chia-Yuan Chang, Yao-Wen Chang, Iris Hui-...
ICCAD
1997
IEEE
137views Hardware» more  ICCAD 1997»
13 years 9 months ago
Optimization techniques for high-performance digital circuits
The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically...
Chandramouli Visweswariah