41 search results - page 1 / 9 » Fast, Accurate and Detailed NoC Simulations |
NOCS
2007
IEEE
13 years 11 months ago
2007
IEEE
Network-on-Chip (NoC) architectures have a wide variety of parameters that can be adapted to the designer’s requirements. Fast exploration of this parameter space is only possib...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
We address the design of complex monolithic systems, where processing cores generate and consume a varying and large amount of data, thus bringing the communication links to the e...
DSD
2006
IEEE
13 years 10 months ago
2006
IEEE
We propose a power model for the Nostrum NoC. For this purpose an empirical power model of links and switches has been formulated and validated with the Synopsys Power Compiler. T...
IPPS
2007
IEEE
13 years 11 months ago
2007
IEEE
In this paper we describe a sequential simulation method to simulate large parallel homo- and heterogeneous systems on a single FPGA. The method is applicable for parallel systems...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...