8 search results - page 2 / 2 » Fast Algorithms for Static Compaction of Sequential Circuit ... |
DATE
1999
IEEE
13 years 9 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
ICCD
2003
IEEE
14 years 2 months ago
2003
IEEE
We discuss the compaction of independent test sequences for sequential circuits. Our first contribution is the formulation of this problem as an integer program, which we then so...
ICCAD
1998
IEEE
13 years 9 months ago
1998
IEEE
A method is presented for identifying primitive path-delay faults in non-scan sequential circuits and generating robust tests for all robustly testable primitive faults. It uses t...