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1999
IEEE

FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy

9 years 4 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits. Our approach combines a conventional ATPG algorithm, a technique based on the frozen clock testing strategy, and a dynamic compaction method based on a genetic algorithm. The frozen clock strategy temporarily suspends the sequential behavior of the circuit by stopping its clock and applying several vectors to increase the number of faults detected without changing the circuit state. Results show that test sets generated using the new approach are more compact than those generated by previous approaches for many circuits.
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where DATE
Authors Yanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici
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