58 search results - page 11 / 12 » Fast Optimal Task Graph Scheduling by Means of an Optimized ... |
ICASSP
2008
IEEE
13 years 11 months ago
2008
IEEE
Multiple memory banks design is employed in many high performance DSP processors. This architectural feature supports higher memory bandwidth by allowing multiple data memory acce...
CP
2008
Springer
13 years 7 months ago
2008
Springer
The Cell BE processor provides both scalable computation power and flexibility, and it is already being adopted for many computational intensive applications like aerospace, defens...
ICRA
2010
IEEE
13 years 3 months ago
2010
IEEE
— The latency of a perception system is crucial for a robot performing interactive tasks in dynamic human environments. We present MOPED, a fast and scalable perception system fo...
ICS
2007
Tsinghua U.
13 years 11 months ago
2007
Tsinghua U.
Increased complexity of memory systems to ameliorate the gap between the speed of processors and memory has made it increasingly harder for compilers to optimize an arbitrary code...
IPPS
2009
IEEE
13 years 12 months ago
2009
IEEE
Modeling communications in wireless networks is a challenging task since it asks for a simple mathematical object on which efficient algorithms can be designed, but that must also...