Sciweavers

32 search results - page 2 / 7
» Fast Sequential Circuit Test Generation Using High-Level and...
Sort
View
VTS
1997
IEEE
96views Hardware» more  VTS 1997»
13 years 9 months ago
Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors
Two fast algorithms for static test sequence compaction are proposed for sequential circuits. The algorithms are based on the observation that test sequences traverse through a sm...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
DATE
1997
IEEE
109views Hardware» more  DATE 1997»
13 years 9 months ago
Sequential circuit test generation using dynamic state traversal
A new method for state justi cation is proposed for sequential circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is use...
Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. P...
ICCAD
1998
IEEE
122views Hardware» more  ICCAD 1998»
13 years 9 months ago
Dynamic fault collapsing and diagnostic test pattern generation for sequential circuits
In this paper, we present results for significantly improving the performance of sequential circuit diagnostic test pattern generation (DATPG). Our improvements are achieved by de...
Vamsi Boppana, W. Kent Fuchs
DATE
1998
IEEE
74views Hardware» more  DATE 1998»
13 years 9 months ago
State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits
We extend the subsequence removal technique to provide signi cantly higher static compaction for sequential circuits. We show that state relaxation techniques can be used to ident...
Michael S. Hsiao, Srimat T. Chakradhar
ATS
2000
IEEE
145views Hardware» more  ATS 2000»
13 years 9 months ago
Compaction-based test generation using state and fault information
We present a new test generation procedure for sequential circuits using newly traversed state and newly detected fault information obtained between successive iterations of vecto...
Ashish Giani, Shuo Sheng, Michael S. Hsiao, Vishwa...