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FPGA
2010
ACM
359views FPGA» more  FPGA 2010»
14 years 2 months ago
Towards scalable placement for FPGAs
Placement based on simulated annealing is in dominant use in the FPGA community due to its superior quality of result (QoR). However, given the progression of FPGA device capacity...
Huimin Bian, Andrew C. Ling, Alexander Choong, Jia...
MICRO
2003
IEEE
258views Hardware» more  MICRO 2003»
13 years 10 months ago
LLVA: A Low-level Virtual Instruction Set Architecture
A virtual instruction set architecture (V-ISA) implemented via a processor-specific software translation layer can provide great flexibility to processor designers. Recent examp...
Vikram S. Adve, Chris Lattner, Michael Brukman, An...
BIBE
2007
IEEE
127views Bioinformatics» more  BIBE 2007»
13 years 11 months ago
A Heuristic for Phylogenetic Reconstruction Using Transposition
Abstract—Because of the advent of high-throughput sequencing and the consequent reduction in cost of sequencing, many organisms have been completely sequenced and most of their g...
Feng Yue, Meng Zhang, Jijun Tang
ICNP
2007
IEEE
13 years 11 months ago
HEXA: Compact Data Structures for Faster Packet Processing
—Data structures representing directed graphs with edges labeled by symbols from a finite alphabet are used to implement packet processing algorithms used in a variety of network...
Sailesh Kumar, Jonathan S. Turner, Patrick Crowley...
SIGCOMM
1999
ACM
13 years 9 months ago
Routing with a Clue
We suggest a new simple forwarding technique to speed-up IP destination address lookup. The technique is a natural extension of IP, requires 5 bits in the IP header (IPv4, 7 in IP...
Anat Bremler-Barr, Yehuda Afek, Sariel Har-Peled