Sciweavers

Share
35 search results - page 1 / 7
» Fast power network analysis with multiple clock domains
Sort
View
ICCD
2007
IEEE
121views Hardware» more  ICCD 2007»
11 years 8 months ago
Fast power network analysis with multiple clock domains
This paper proposes an efficient analysis flow and an algorithm to identify the worst case noise for power networks with multiple clock domains. First, we apply the Laplace transf...
Wanping Zhang, Ling Zhang, Rui Shi, He Peng, Zhi Z...
FPGA
2006
ACM
111views FPGA» more  FPGA 2006»
11 years 3 months ago
FPGA clock network architecture: flexibility vs. area and power
This paper examines the tradeoffs between flexibility, area, and power dissipation of programmable clock networks for FieldProgrammable Gate Arrays (FPGA's). The paper begins...
Julien Lamoureux, Steven J. E. Wilton
MICRO
2002
IEEE
108views Hardware» more  MICRO 2002»
11 years 4 months ago
Dynamic frequency and voltage control for a multiple clock domain microarchitecture
We describe the design, analysis, and performance of an on–line algorithm to dynamically control the frequency/voltage of a Multiple Clock Domain (MCD) microarchitecture. The MC...
Greg Semeraro, David H. Albonesi, Steve Dropsho, G...
DAC
2008
ACM
12 years 21 days ago
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
Ümit Y. Ogras, Diana Marculescu, Radu Marcule...
HPCA
2005
IEEE
12 years 2 days ago
Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors
Dynamic voltage and frequency scaling (DVFS) is a widely-used method for energy-efficient computing. In this paper, we present a new intra-task online DVFS scheme for multiple clo...
Qiang Wu, Philo Juang, Margaret Martonosi, Douglas...
books