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2006
IEEE
102views Hardware» more  DATE 2006»
13 years 11 months ago
Faster exploration of high level design alternatives using UML for better partitions
Partitioning is a time consuming and computationally complex optimization problem in the codesign of hardware software systems. The stringent time-to-market requirements have resu...
Waseem Ahmed, Doug Myers
FMAM
2010
157views Formal Methods» more  FMAM 2010»
13 years 2 months ago
An Experience on Formal Analysis of a High-Level Graphical SOA Design
: In this paper, we present the experience gained with the participation in a case study in which a novel high-level design language (UML4SOA) was used to produce a service-oriente...
Maurice H. ter Beek, Franco Mazzanti, Aldi Sulova
RTCSA
2007
IEEE
13 years 11 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) met...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali...
ISPASS
2005
IEEE
13 years 10 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...
SAMOS
2004
Springer
13 years 10 months ago
Scalable Instruction-Level Parallelism.
This paper presents a model for instruction-level distributed computing that allows the implementation of scalable chip multiprocessors. Based on explicit microthreading it serves ...
Chris R. Jesshope