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2007
IEEE

An MPSoC Performance Estimation Framework Using Transaction Level Modeling

9 years 6 months ago
An MPSoC Performance Estimation Framework Using Transaction Level Modeling
— To use the tremendous hardware resources available in next generation MultiProcessor Systems-on-Chip (MPSoC) efficiently, rapid and accurate design space exploration (DSE) methods are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of the timed Programmer’s View (PVT) level by introducing two complementary modeling sublevels. The first one, PVT Transaction Accurate (PVT-TA), offers a high simulation speedup factor over the Cycle Accurate Bit Accurate (CABA) level modeling. The second one, PVT Event Accurate (PVT-EA), provides a better accuracy with a still acceptable speedup factor. An MPSoC platform has been developed using these two sublevels including performance estimation models. Simulation resul...
Rabie Ben Atitallah, Smaïl Niar, Samy Meftali
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where RTCSA
Authors Rabie Ben Atitallah, Smaïl Niar, Samy Meftali, Jean-Luc Dekeyser
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