50 search results - page 4 / 10 » Fault tolerance in cellular automata at high fault rates |
ATS
2000
IEEE
13 years 10 months ago
2000
IEEE
At very high frequencies, the major potential of asynchronous circuits is absence of clock skew and, through that, better exploitation of relative timing relations. This paper pre...
CGO
2005
IEEE
13 years 12 months ago
2005
IEEE
To improve performance and reduce power, processor designers employ advances that shrink feature sizes, lower voltage levels, reduce noise margins, and increase clock rates. Howev...
IEEEPACT
2007
IEEE
14 years 17 days ago
2007
IEEE
Continued scaling of CMOS technology to smaller transistor sizes makes modern processors more susceptible to both transient and permanent hardware faults. Circuitlevel techniques ...
TC
2010
13 years 4 months ago
2010
—The number of CPUs in chip multiprocessors is growing at the Moore’s Law rate, due to continued technology advances. However, new technologies pose serious reliability challen...
ISQED
2007
IEEE
14 years 16 days ago
2007
IEEE
Abstract—A Network-on-Chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected...