75 search results - page 13 / 15 » Fault tolerant methods for reliability in FPGAs |
SBCCI
2004
ACM
13 years 11 months ago
2004
ACM
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
TWC
2008
13 years 5 months ago
2008
Abstract-- This work proposes a novel fault-tolerant classification system based on distributed detection and two-dimensional channel coding. A rule is then derived to reduce the s...
DSN
2002
IEEE
13 years 10 months ago
2002
IEEE
Concentration of design effort for current single-chip Commercial-Off-The-Shelf (COTS) microprocessors has been directed towards performance. Reliability has not been the primary ...
SC
2009
ACM
14 years 17 days ago
2009
ACM
We present ECC FIFO, a mechanism enabling two-tiered last-level cache error protection using an arbitrarily strong tier-2 code without increasing on-chip storage. Instead of addin...
CASES
2006
ACM
13 years 9 months ago
2006
ACM
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...