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ISCA
1995
IEEE
98views Hardware» more  ISCA 1995»
13 years 9 months ago
Instruction Fetching: Coping with Code Bloat
Previous research has shown that the SPEC benchmarks achieve low miss ratios in relatively small instruction caches. This paper presents evidence that current software-development...
Richard Uhlig, David Nagle, Trevor N. Mudge, Stuar...
ATAL
2009
Springer
13 years 9 months ago
Effective bidding and deal identification for negotiations in highly nonlinear scenarios
Most real-world negotiation scenarios involve multiple, interdependent issues. These scenarios are specially challenging because the agents' utility functions are nonlinear, ...
Ivan Marsá-Maestre, Miguel A. López-...
CODES
2005
IEEE
13 years 11 months ago
DVS for buffer-constrained architectures with predictable QoS-energy tradeoffs
We present a new scheme for dynamic voltage and frequency scaling (DVS) for processing multimedia streams on architectures with restricted buffer sizes. The main advantage of our ...
Alexander Maxiaguine, Samarjit Chakraborty, Lothar...
RTAS
2006
IEEE
13 years 11 months ago
Bounding Preemption Delay within Data Cache Reference Patterns for Real-Time Tasks
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
RTSS
2006
IEEE
13 years 11 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller