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» Finite Field Multiplier Using Redundant Representation
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TCAD
2002
139views more  TCAD 2002»
13 years 5 months ago
Digital filter synthesis based on an algorithm to generate all minimal signed digit representations
In this paper, the authors propose an algorithm to find all the minimal signed digit (MSD) representations of a constant and present an algorithm to synthesize digital filters base...
In-Cheol Park, Hyeong-Ju Kang
ARITH
2009
IEEE
14 years 12 days ago
Fully Redundant Decimal Arithmetic
Hardware implementation of all the basic radix-10 arithmetic operations is evolving as a new trend in the design and implementation of general purpose digital processors. Redundan...
Saeid Gorgin, Ghassem Jaberipur
TC
2008
13 years 5 months ago
Automatic Generation of Modular Multipliers for FPGA Applications
Since redundant number systems allow for constant time addition, they are often at the heart of modular multipliers designed for public key cryptography (PKC) applications. Indeed,...
Jean-Luc Beuchat, Jean-Michel Muller
FDTC
2006
Springer
80views Cryptology» more  FDTC 2006»
13 years 9 months ago
Robust Finite Field Arithmetic for Fault-Tolerant Public-Key Cryptography
We present a new approach to fault tolerant public key cryptography based on redundant arithmetic in finite rings. Redundancy is achieved by embedding non-redundant field or ring ...
Gunnar Gaubatz, Berk Sunar
ARITH
2007
IEEE
13 years 12 months ago
A New Family of High.Performance Parallel Decimal Multipliers
This paper introduces two novel architectures for parallel decimal multipliers. Our multipliers are based on a new algorithm for decimal carry–save multioperand addition that us...
Álvaro Vázquez, Elisardo Antelo, Pao...