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» Fixed-Polynomial Size Circuit Bounds
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PATMOS
2005
Springer
13 years 11 months ago
Closed-Form Bounds for Interconnect-Aware Minimum-Delay Gate Sizing
Early circuit performance estimation and easy-to-apply methods for minimum-delay gate sizing are needed, in order to enhance circuit’s performance and to increase designers’ pr...
Giorgos Dimitrakopoulos, Dimitris Nikolos
ICALP
2009
Springer
14 years 5 months ago
Bounds on the Size of Small Depth Circuits for Approximating Majority
In this paper, we show that for every constant 0 < < 1/2 and for every constant d 2, the minimum size of a depth d Boolean circuit that -approximates Majority function on n ...
Kazuyuki Amano
FOCS
2007
IEEE
13 years 11 months ago
A Lower Bound for the Size of Syntactically Multilinear Arithmetic Circuits
We construct an explicit polynomial f(x1, . . . , xn), with coefficients in {0, 1}, such that the size of any syntactically multilinear arithmetic circuit computing f is at least ...
Ran Raz, Amir Shpilka, Amir Yehudayoff
APPROX
2008
Springer
79views Algorithms» more  APPROX 2008»
13 years 7 months ago
Derandomizing the Isolation Lemma and Lower Bounds for Circuit Size
Vikraman Arvind, Partha Mukhopadhyay