578 search results - page 2 / 116 » Flow Map Layout |
DSD
2010
IEEE
13 years 2 months ago
2010
IEEE
We present a high-level synthesis flow for mapping an algorithm description (in C) to a provably equivalent registertransfer level (RTL) description of hardware. This flow uses an ...
DAC
2004
ACM
14 years 5 months ago
2004
ACM
With the advent of deep-submicron technologies, it has become essential to model the impact of physical/layout effects up front in all design flows [1]. The effect of layout paras...
ICRA
2003
IEEE
13 years 10 months ago
2003
IEEE
- In this paper we describe the navigation and planning of the i-Fork system, a flexible AGV intended to operate in partially structured warehouses where frequent floor plant layou...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
One of the major roadblocks in reduction of library generation cycle time is the layout generation phase. The two methods of doing automatic layout generation are synthesis and mig...
DIAGRAMS
2008
Springer
13 years 6 months ago
2008
Springer
Research on effective algorithms for efficient graph layout continues apace, and faster technology has led to increasing research on algorithms for the depiction of dynamic graphs ...