176 search results - page 2 / 36 » Formal Verification of Gate-Level Computer Systems |
VLSID
2003
IEEE
14 years 5 months ago
2003
IEEE
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
ICSE
2008
IEEE-ACM
14 years 5 months ago
2008
IEEE-ACM
We report on the successful application of academic experience with formal modelling and verification techniques to an automotive scenario from the service-oriented computing doma...
DAC
1997
ACM
13 years 8 months ago
1997
ACM
We present our experiences with the formal verification of an automotive chip used to control the safety features in a car. We used a BDD based model checker in our work. We descr...
ENTCS
2006
13 years 4 months ago
2006
In this paper we investigate how formal software verification systems can be improved by utilising parallel assignment in weakest precondition computations.
ICCS
2007
Springer
13 years 8 months ago
2007
Springer
In this paper, we show how symbolic algebra in Mathematica can be used to formally verify analog and mixed signal designs. The verification methodology is based on combining induct...