176 search results - page 3 / 36 » Formal Verification of Gate-Level Computer Systems |
FLAIRS
2000
13 years 6 months ago
2000
Behaviour of systems is described by formal languages: the sets of all sequences of actions. Regarding ion, alphabetic language homomorphisms are compute abstract behaviours. To a...
HASE
2008
IEEE
13 years 5 months ago
2008
IEEE
Designing safety-critical systems is a complex process, and especially when the design is carried out at different f abstraction where the correctness of the design at one level i...
HYBRID
1998
Springer
13 years 9 months ago
1998
Springer
This paper investigates how formal techniques can be used for the analysis and verification of hybrid systems [1,5,7,16] -- systems involving both discrete and continuous behavior....
DFG
2004
Springer
13 years 9 months ago
2004
Springer
This paper presents the real-time model checker RAVEN and related theoretical background. RAVEN augments the efficiency of traditional symbolic model checking with possibilities to...
DAC
1996
ACM
13 years 9 months ago
1996
ACM
We present a formal verification methodology that we have used on a computer system design project. The methodology integrates a temporal logic model checker with a conventional pr...