19 search results - page 1 / 4 » Formal Verification of a DSP Chip Using an Iterative Approac... |
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...
ASYNC
2007
IEEE
13 years 9 months ago
2007
IEEE
Few formal verification techniques are currently available for asynchronous designs. In this paper, we describe a new approach for the formal verification of asynchronous architec...
DAC
2000
ACM
14 years 6 months ago
2000
ACM
Contemporary microprocessors implement many iterative algorithms. For example, the front-end of a microprocessor repeatedly fetches and decodes instructions while updating interna...
DAC
2006
ACM
13 years 11 months ago
2006
ACM
Architectural decisions for DSP modules are often analyzed using high level C models. Such high-level explorations allow early examination of the algorithms and the architectural ...
FMCAD
2007
Springer
13 years 11 months ago
2007
Springer
— The concept of applying partial fencing to logic built-in self test (LBIST) hardware structures for the purpose of using partially good chips is well known in the chip design i...