34 search results - page 1 / 7 » Formal hardware verification by integrating HOL and MDG |
GLVLSI
2000
IEEE
13 years 9 months ago
2000
IEEE
MJ
2006
13 years 5 months ago
2006
In this paper, we describe a hybrid tool for hardware formal verification that links the HOL (higher-order logic) theorem prover and (multiway decision graphs) model checker. Our ...
ATVA
2004
Springer
13 years 9 months ago
2004
Springer
While model checking suffers from the state space explosion problem, theorem proving is quite tedious and impractical for verifying complex designs. In this work, we present a veri...
CIIA
2009
13 years 6 months ago
2009
Abstract. Formal verification of digital systems is achieved, today, using one of two main approaches: states exploration (mainly model checking and equivalence checking) or deduct...
DSD
2002
IEEE
13 years 10 months ago
2002
IEEE
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and stru...