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» Formal methods: the very idea - Some thoughts about why they...
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FMICS
2006
Springer
13 years 9 months ago
SAT-Based Verification of LTL Formulas
Abstract. Bounded model checking (BMC) based on satisfiability testing (SAT) has been introduced as a complementary technique to BDDbased symbolic model checking of LTL properties ...
Wenhui Zhang
MEMOCODE
2006
IEEE
13 years 11 months ago
Latency-insensitive design and central repetitive scheduling
The theory of latency-insensitive design (LID) was recently invented to cope with the time closure problem in otherwise synchronous circuits and programs. The idea is to allow the...
Julien Boucaron, Robert de Simone, Jean-Vivien Mil...