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» Formal verification: is it real enough
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DAC
2005
ACM
13 years 6 months ago
Formal verification: is it real enough?
Yaron Wolfsthal, Rebecca M. Gott
VLSID
2003
IEEE
180views VLSI» more  VLSID 2003»
14 years 5 months ago
Automating Formal Modular Verification of Asynchronous Real-Time Embedded Systems
Most verification tools and methodologies such as model checking, equivalence checking, hardware verification, software verification, and hardware-software coverification often fl...
Pao-Ann Hsiung, Shu-Yu Cheng
DAC
2001
ACM
14 years 5 months ago
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukul...
CAV
2007
Springer
227views Hardware» more  CAV 2007»
13 years 8 months ago
The TASM Toolset: Specification, Simulation, and Formal Verification of Real-Time Systems
Abstract. In this paper, we describe the features of the Timed Abstract State Machine toolset. The toolset implements the features of the Timed Abstract State Machine (TASM) langua...
Martin Ouimet, Kristina Lundqvist