105 search results - page 2 / 21 » Formal verification: is it real enough |
FDL
2003
IEEE
13 years 10 months ago
2003
IEEE
APSEC
2001
IEEE
13 years 9 months ago
2001
IEEE
GLVLSI
2007
IEEE
13 years 9 months ago
2007
IEEE
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
FTRTFT
1992
Springer
13 years 9 months ago
1992
Springer
Real-Time Logic is a formal notation for reasoning about temporal behaviour. Z is a general purpose specification language, but lacks explicit features for expressing real-time co...
ISORC
2000
IEEE
13 years 8 months ago
2000
IEEE
The Unified Modeling Language UML is well-suited for the design of real-time systems. In particular, the design of dynamic system behaviors is supported by interaction diagrams an...