38 search results - page 2 / 8 » Formal verification of LTL formulas for SystemC designs |
MEMOCODE
2010
IEEE
13 years 3 months ago
2010
IEEE
Electronic System Level (ESL) design manages the complexity of todays systems by using abstract models. In this context Transaction Level Modeling (TLM) is state-of-theart for desc...
CODES
2008
IEEE
13 years 7 months ago
2008
IEEE
SystemC is widely used for modeling and simulation in hardware/software co-design. Due to the lack of a complete formal semantics, it is not possible to verify SystemC designs. In...
ATVA
2006
Springer
13 years 9 months ago
2006
Springer
Of special interest in formal verification are safety properties, which assert that the system always stays within some allowed region. Each safety property can be associated with...
FM
2008
Springer
13 years 6 months ago
2008
Springer
TLM (Transaction-Level Modeling) was introduced to cope with the increasing complexity of Systems-on-Chip designs by raising the modeling level. Currently, TLM is primarily used fo...
ASE
2005
13 years 5 months ago
2005
Techniques for efficiently evaluating future time Linear Temporal Logic (abbreviated LTL) formulae on finite execution traces are presented. While the standard models of LTL are i...