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» Formal verification of LTL formulas for SystemC designs
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FDL
2004
IEEE
13 years 9 months ago
A Functional Programming Framework of Heterogeneous Model of Computation for System Design
System-on-Chip (SOC) and other complex distributed hardware/software systems contain heterogeneous components such as DSPs, micro-controllers, application specific logic etc., whi...
Deepak Mathaikutty, Hiren D. Patel, Sandeep K. Shu...
CONCUR
2001
Springer
13 years 9 months ago
Extended Temporal Logic Revisited
A key issue in the design of a model-checking tool is the choice of the formal language with which properties are specified. It is now recognized that a good language should exten...
Orna Kupferman, Nir Piterman, Moshe Y. Vardi
DAC
2007
ACM
13 years 9 months ago
Automotive Software Integration
A growing number of networked applications is implemented on increasingly complex automotive platforms with several bus standards and gateways. Together, they challenge the automo...
Razvan Racu, Arne Hamann, Rolf Ernst, Kai Richter