Sciweavers

14 search results - page 2 / 3
» Formal verification of iterative algorithms in microprocesso...
Sort
View
ISPD
1997
ACM
100views Hardware» more  ISPD 1997»
13 years 9 months ago
A pseudo-hierarchical methodology for high performance microprocessor design
- This paper reports on a highly effective methodology to construct complex high performance microprocessors. Critical aspects of the methodology include an integrated database for...
A. Bertolet, K. Carpenter, Keith M. Carrig, Albert...
DAC
2001
ACM
14 years 6 months ago
Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
Dong Wang, Pei-Hsin Ho, Jiang Long, James H. Kukul...
ESOP
2010
Springer
14 years 2 months ago
Formal Verification of Coalescing Graph-Coloring Register Allocation
Iterated Register Coalescing (IRC) is a widely used heuristic for performing register allocation via graph coloring. Many implementations in existing compilers follow (more or less...
Andrew W. Appel, Benoît Robillard, Sandrine ...
ICTAC
2010
Springer
13 years 2 months ago
Mechanized Verification with Sharing
We consider software verification of imperative programs by theorem proving in higher-order separation logic. Of particular interest are the difficulties of encoding and reasoning ...
J. Gregory Malecha, Greg Morrisett
DATE
2000
IEEE
132views Hardware» more  DATE 2000»
13 years 9 months ago
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience
In current microprocessors and systems, an increasingly high silicon portion is derived through automatic synthesis, with designers working exclusively at the RT-level, and design...
Fulvio Corno, Matteo Sonza Reorda, Giovanni Squill...