12 search results - page 2 / 3 » Formal verification of pipeline conflicts in RISC processors |
DAC
1997
ACM
13 years 9 months ago
1997
ACM
Abstract. Many modern systems are designed as a set of interconnected reactive subsystems. The subsystem verification task is to verify an implementation of the subsystem against t...
CAV
1998
Springer
13 years 9 months ago
1998
Springer
We present a two-part approach for verifying out-of-order execution. First, the complexity of out-of-order issue and scheduling is handled by creating der abstraction of the out-of...
IEEEPACT
2007
IEEE
13 years 11 months ago
2007
IEEE
The process of verifying a new microprocessor is a major problem for the computer industry. Currently, architects design processors to be fast, power-efficient, and reliable. Howe...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
Verification is one of the most complex and expensive tasks in the current Systems-on-Chip (SOC) design process. Many existing approaches employ a bottom-up approach to pipeline v...
FAC
2000
13 years 5 months ago
2000
In this paper we present a method of describing microprocessors at different levels of temporal and data abstraction. We consider microprogrammed, pipelined and superscalar proces...