Sciweavers

Share
2 search results - page 1 / 1
» FreezeFrame: Compact Test Generation Using a Frozen Clock St...
Sort
View
DATE
1999
IEEE
120views Hardware» more  DATE 1999»
11 years 11 months ago
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...
Yanti Santoso, Matthew C. Merten, Elizabeth M. Rud...
JISE
2000
71views more  JISE 2000»
11 years 6 months ago
Compact Test Generation Using a Frozen Clock Testing Strategy
Elizabeth M. Rudnick, Miron Abramovici
books