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CEC
2005
IEEE
13 years 10 months ago
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
Testing of VLSI circuits can cause generation of excessive heat which can damage the chips under test. In the random testing environment, high-performance CMOS circuits consume sig...
Artem Sokolov, Alodeep Sanyal, L. Darrell Whitley,...
CORR
2010
Springer
152views Education» more  CORR 2010»
13 years 2 months ago
Evolutionary Approach to Test Generation for Functional BIST
In the paper, an evolutionary approach to test generation for functional BIST is considered. The aim of the proposed scheme is to minimize the test data volume by allowing the dev...
Y. A. Skobtsov, D. E. Ivanov, V. Y. Skobtsov, Raim...
ITC
1996
IEEE
98views Hardware» more  ITC 1996»
13 years 9 months ago
Mixed-Mode BIST Using Embedded Processors
Abstract. In complex systems, embedded processors may be used to run software routines for test pattern generation and response evaluation. For system components which are not comp...
Sybille Hellebrand, Hans-Joachim Wunderlich, Andre...
IFIP
2001
Springer
13 years 9 months ago
Functional Test Generation using Constraint Logic Programming
— Semi-formal verification based on symbolic simulation offers a good compromise between formal model checking and numerical simulation. The generation of functional test vector...
Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre
ICTAC
2004
Springer
13 years 10 months ago
Combining Algebraic and Model-Based Test Case Generation
Abstract. The classical work on test case generation and formal methods focuses either on algebraic or model-based specifications. In this paper we propose an approach to derive t...
Li Dan, Bernhard K. Aichernig