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ICCAD
1997
IEEE
171views Hardware» more  ICCAD 1997»
13 years 9 months ago
The disjunctive decomposition of logic functions
In this paper we present an algorithm for converting a BDD representation of a logic function into a multiple-level netlist of disjoint-support subfunctions. On the theoretical si...
Valeria Bertacco, Maurizio Damiani
DAC
2001
ACM
14 years 5 months ago
An Algorithm for Bi-Decomposition of Logic Functions
We propose a new BDD-based method for decomposition of multi-output incompletely specified logic functions into netlists of two-input logic gates. The algorithm uses the internal ...
Alan Mishchenko, Bernd Steinbach, Marek A. Perkows...
ICFP
2008
ACM
14 years 4 months ago
Functional netlists
In efforts to overcome the complexity of the syntax and the lack of formal semantics of conventional hardware description languages, a number of functional hardware description la...
Sungwoo Park, Jinha Kim, Hyeonseung Im
ISCAS
2003
IEEE
119views Hardware» more  ISCAS 2003»
13 years 10 months ago
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning
In this paper, the Simulated Evolution algorithm (SimE) is engineered to solve the optimization problem of multi-objective VLSI netlist bi-partitioning. The multi-objective versio...
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
ICCAD
1994
IEEE
101views Hardware» more  ICCAD 1994»
13 years 9 months ago
A general framework for vertex orderings, with applications to netlist clustering
We present a general framework for the construction of vertex orderings for netlist clustering. Our WINDOW algorithm constructs an ordering by iteratively adding the vertex with h...
Charles J. Alpert, Andrew B. Kahng