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ICCD
1995
IEEE
119views Hardware» more  ICCD 1995»
13 years 8 months ago
Extraction of finite state machines from transistor netlists by symbolic simulation
– This paper describes a new technique for extracting clock-level finite state machines(FSMs) from transistor netlists using symbolic simulation. The transistor netlist is prepr...
Manish Pandey, Alok Jain, Randal E. Bryant, Derek ...
EAAI
2006
189views more  EAAI 2006»
13 years 4 months ago
Evolutionary algorithms for VLSI multi-objective netlist partitioning
The problem of partitioning appears in several areas ranging from VLSI, parallel programming, to molecular biology. The interest in finding an optimal partition especially in VLSI ...
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Aba...
ICCAD
1997
IEEE
121views Hardware» more  ICCAD 1997»
13 years 9 months ago
Adaptive methods for netlist partitioning
An algorithm that remains in use at the core of many partitioning systems is the Kernighan-Lin algorithm and a variant the Fidducia-Matheysses (FM) algorithm. To understand the FM...
Wray L. Buntine, Lixin Su, A. Richard Newton, Andr...
ASPDAC
1999
ACM
122views Hardware» more  ASPDAC 1999»
13 years 9 months ago
A Clustering Based Linear Ordering Algorithm for K-Way Spectral Partitioning
The spectral method can lead to a high quality of multi-way partition due to its ability to capture global netlist information. For spectral partition, n netlist modules are mappe...
Shiuann-Shiuh Lin, Wen-Hsin Chen, Wen-Wei Lin, Tin...
ISPD
1997
ACM
105views Hardware» more  ISPD 1997»
13 years 9 months ago
Regular layout generation of logically optimized datapaths
The inherent distortion of the structural regularity of VLSI datapaths after logic optimization has until now precluded dense regular layouts of optimized datapaths despite their ...
R. X. T. Nijssen, C. A. J. van Eijk