138 search results - page 1 / 28 » Functional test generation for delay faults in combinational... |
TODAES
1998
13 years 4 months ago
1998
MEMOCODE
2007
IEEE
13 years 11 months ago
2007
IEEE
Due to the rapidly growing speed and the decreasing size of gates in modern chips, the probability of faults caused by the production process grows. Already small variations lead ...
VLSID
1995
IEEE
13 years 8 months ago
1995
IEEE
ICCAD
1994
IEEE
13 years 9 months ago
1994
IEEE
We consider the problem of testing for delay faults in macrobased circuits. Macro-based circuits are obtained as a result of technology mapping. Gate-level fault models cannot be ...
DATE
2007
IEEE
13 years 11 months ago
2007
IEEE
A high-level test synthesis (HLTS) method targeted for delay fault testability is presented. The proposed method, when combined with hierarchical test pattern generation for embed...